The present invention relates to an open-loop biasing circuit for biasing a magnetoresistive element. In particular, the present invention relates to an open-loop biasing circuit with improved power supply and common mode rejection.
The present invention is typically used in a computer disc drive as part of a "read" channel that includes a magnetic-field sensing element used to "read" information stored on a magnetic disc. The information is stored on the disc as a series of small magnetic domains which produce a series of small localized magnetic fields. To "read" the stored information, the sensing element passes over the disc and creates an electrical signal based on the direction of the magnetic fields. The remainder of the read channel converts the electrical signal into a digital signal that is decoded to reproduce the stored information.
One type of sensing element, known as a magnetoresistive or MR head, "reads" the stored magnetic information by measuring changes in the electrical resistance of a material within the head as the head passes through the magnetic fields. To convert the changes in resistance into a usable voltage signal, MR heads are typically biased with a current that creates a voltage drop across the resistive portion of the MR head. Ideally, the bias current is controlled so that any changes in the voltage drop across the MR head are attributed to changes in the resistance of the head. Thus, when the head is properly biased, the voltage across the head tracks the changes in the magnetic fields, making the voltage useful as a read signal.
Often, the voltage across the MR head is amplified by a differential amplifier. To improve the linearity of the differential amplifier, it is advantageous if the MR head is biased so that the MR head's two terminals have the same voltage magnitude but opposite voltage polarity from each other. When the MR head is biased in this manner, an increase in the resistance of the MR head due to a magnetic field causes an increase in the voltage of one terminal of the head and an equivalent decrease in the voltage of the other terminal of the head.
This type of biasing can be achieved using two different current sources, one coupled to each terminal of the MR head. The current sources and any additional biasing components, must be balanced relative to the MR head, so that the same magnitude voltage is developed at each terminal of the MR head. Thus, not only must the current sources create the same amount of current, but the impedance seen by one terminal of the MR head must be identical to the impedance seen by the other terminal of the MR head at all relevant frequencies (DC--200 MHz).
In some prior art biasing circuits, feedback loops have been used to keep the terminal voltages of the MR head centered about ground. These feedback loops use the voltages at the terminals of the MR head to control one of the current sources so that the voltages at the terminals are kept centered about ground. Although such feedback loops can be effective, they require a large number of devices to implement and are hampered by an inherent feedback loop delay.
In addition to having balanced current and resistive elements, the two terminals of the MR head should have matching frequency responses so as to remove any noise that is common to both current sources. In other words, an input noise signal that is common to both current sources should produce the same voltage increase or decrease at the two terminals of the MR head. If both terminals increase or decrease together, the voltage drop across the MR head remains the same and the common noise is not amplified. Common noise that is not amplified is considered suppressed or rejected, and this type of reaction to common noise is known as common mode rejection.
In MR head biasing circuits, common mode rejection is dependent on the capacitance seen by each terminal of the MR head since such capacitance determines the frequency response of each terminal. If one terminal sees more capacitance than the other terminal, the voltage at one terminal will change slower than the voltage at the other terminal for a given common noise signal. This will cause the common noise to be amplified by the differential amplifier and thereby will cause a deterioration of common mode rejection.
A second type of noise suppression is known as power supply rejection. This type of noise suppression attempts to eliminate noise that is found in only one of the two current or power sources.
In bias circuits that use feedback loops, power supply noise is reduced by monitoring the MR head's terminals for voltage offsets caused by power supply noise. If an offset is detected, the feedback loop is used to adjust one of the two current sources based on the offset voltage at the terminals of the head. By modifying one of the current sources, the voltage offset may be negated. Although such feedback circuits are effective at removing some noise frequencies, the delays inherent in the feedback loops limit the range of noise frequencies that the loops can suppress.
Power supply rejection can also be achieved by using capacitors. However, off-chip capacitors, those which are not formed within the same integrated circuit as the remainder of the biasing circuit, are expensive to add to the biasing circuit and, sometimes, are a source of additional noise in the circuit. Integrated circuit capacitors, although cheaper and easier to add to MR head biasing circuits, include unwanted parasitic capacitances.
The parasitic capacitances found in integrated circuit capacitors is caused by the physical structure of the capacitor, which is shown in cross-section in FIG. 2. The cross-section of FIG. 2 shows a typical integrated circuit capacitor with three terminal connections: upper-plate connection 20, lower-plate connection 22, and body connection 24. Preferably, all three terminal connections are composed of a metallic material. Upper-plate connection 20 has a large surface area composed of a width in the horizontal direction of FIG. 2 and a length in the direction orthogonal to the page of FIG. 2. This surface area allows upper-plate connection 20 to act as one plate of the capacitor.
Extending below the entirety of upper-plate connection 20 is insulating material 26. Insulating material 26 is typically formed as a single layer during the production of the capacitor. After insulating material 26 has been deposited, portions of the material are removed to provide openings so that lower-plate connection 22 and body connection 24 can make contact with parts of the capacitor located below insulating material 26.
Below insulating material 26, and extending under upper-plate connection 20 and lower-plate connection 22, is lower plate 30. Lower plate 30 is separated from upper-plate connection 20 by insulating material 26, but makes direct contact with lower-plate connection 22. Lower plate 30 is preferably constructed from a P-doped semi-conductor material. Lower plate 30, insulating material 26 and upper-plate connection 20 together form the desired nominal capacitance for this capacitor.
Lower plate 30 is deposited within body 28, also known as the tub. Body 28, which is deposited on a substrate 32, is in direct contact with body connection 24 and is preferably composed of an N-doped semi-conductor material. The fact that body 28 is N-doped and lower plate 30 is P-doped means that there is a P-N junction between lower plate 30 and body 28. This P-N junction creates the parasitic capacitance found in integrated circuit capacitors. Specifically, the P-N junction forms a significant junction capacitance because the P-N junction must be reverse biased at all times to prevent current from flowing from the lower plate to the body. This junction capacitance is not fixed, but instead, increases as the reverse-bias voltage across the junction increases. Thus, the parasitic capacitance is a function of the voltage difference between the body and the lower plate.
This parasitic capacitance makes it difficult to add integrated circuit capacitors to MR head biasing circuits since all of the capacitance added to the circuit must be balanced relative to the two terminals of the MR head to ensure good common mode rejection. Thus, both the nominal capacitance and the parasitic capacitance must be balanced in the circuit so that the two terminals of the MR head have the same frequency response to common noise. In the prior art, this balance has not been achieved, partly because the parasitic capacitance is voltage dependent. In some circuit layouts, this voltage dependence causes one terminal of the MR head to see a larger parasitic capacitance than the other terminal of the MR head, simply because one terminal is at a higher voltage than the other terminal. Thus, it has been difficult to achieve both high power supply and common mode rejection in MR head biasing circuits.